Reconfigurable architecture for arbitrary sample rate conversion in software defined radios

Efficient implementation of the sample rate converter is extremely important to reduce the power consumption of software defined radios. This becomes even more important when sigma delta converters are used for the analog to digital conversion due to the very high oversampling rates involved. In a multistandard radio, the sample rate converter should also be capable of handling variable conversion ratios and channel bandwidths. In this paper we propose a simple scheme to efficiently factorize any large arbitrary factor into integral and fractional factors. We also suggest efficient reconfigurable hardware architectures to implement these conversion factors.