Evaluation of intrinsic parameter fluctuations on 45, 32 and 22nm technology node LP N-MOSFETs

The quantitative evaluation of the impact of key sources of statistical variability (SV) are presented for LP nMOSFETs corresponding to 45 nm, 32 nm and 22 nm technology generation transistors with bulk, thin body (TB) SOI and double gate (DG) device architectures respectively. The simulation results indicate that TBSOI and DG are not only resistant to random dopant induced variability, but also are more tolerant to line edge roughness induced variability. Even two technology generations ahead from their bulk counterparts, DG MOSFETs will still have 4 times less variability than bulk devices.