FPGA-based Equivalent Simulation Technology (FEST) for clustered stream architecture

Stream architecture research is often hindered by slow software simulations. Simulators based on FPGA are much faster. However, larger scale stream architecture simulation needs more FPGA resource, which may result in more FPGA chips or larger capacity FPGA chip would be used. It not only increases the complexity of design, but also increases the cost of research. This paper proposed FPGA-based equivalent simulation technology (FEST) and constructs an Equivalent model called FEST model based on it. FEST can support cluster-scalable simulation for clustered stream architecture well by replace some components by a simpler structure with equivalent function. The simulator based on FEST model (1) needs fewer FPGA resource than the original system but has little influence on simulation speed, (2) is accurate to cycle level resolution, (3) can run unmodified applications, (4) can reappear simulation results including resource consuming and timing analysis of original system.