New findings in nano-scale interface physics and their relations to nano-CMOS technologies

We show the new findings in nano-scale interface physics and atomistic beheviors of defects in gate dielectric materials. In this paper, we first discuss the relation between defect behaviors and transistor characteristics. Next, we introduce our newly prosed mechanism of Fermi level pinning governed by the interface reaction. Further, we show that conventional charge neutrality level concept does not applicable to metal/high-k dielectric interfaces, and we propose a generalized charge neutrality level concept that includes both nano-scale interface structures and metal band structures. Finally, we discuss the atomistic investigation on the characteristics of conventional Si/SiO2 nano interfaces