3D stacking of chips with electrical and microfluidic I/O interconnects

Motivations for three-dimensional (3D) integration include reduction in system size, interconnect delay, power dissipation and enabling hyper-integration of chips fabricated using disparate process technologies. Although various low-power commercial products exploit the advantages of improved performance and increased device packing density realized by 3D stacking of chips (using wirebonds), such technologies are not suitable for high-performance chips due to ineffective power delivery and heat removal. This is important because high performance chips are projected to dissipate more than 100 W/cm
²
and require more than 100 A of supply current. Consequently, when such chips are stacked, the challenges in power delivery and cooling become greatly exacerbated. Thus, revolutionary interconnection and packaging technologies will be needed to address these limits [Bakir, et. al., (2007)]. This paper reports, for the first time, the configuration, fabrication, and experimental results of a 3D integration platform that can support the power delivery, signaling, and heat removal requirements for high-performance chips. The key behind this 3D platform is the ability to process integrate, at the wafer-level, electrical and microfluidic interconnection networks on the wafer containing the electrical circuitry and assemble such chips using conventional flip-chip technology.