Comparison of arithmetic units for asynchronous processors

In the latest studies, utmost attention has been paid to the system throughput in conjunction with low energy consumption. It is achieved by finding and optimizing the longest delays in blocks in a synchronous design. However, this is not necessarily the optimum method for optimizing an asynchronous design, since it is the average delay that defines the throughput rather than the critical path which is seldom activated. Whereas such an optimized logic may perform well in synchronous systems, there should exist a way to fine-tune logic blocks for asynchronous systems as well. In this paper we have used various adder and multiplier architectures to study what kind of conclusions the designer can draw about the applicability of arithmetic logic units based on such figures that are already generally available or can be easily generated.