A 25–75 GHz Miniature Double Balanced Frequency Doubler in 0.18-μm CMOS Technology

A 25–75 GHz compact double balanced frequency doubler fabricated in standard 0.18-μm CMOS process is demonstrated. The resistive doubler is composed of two identical asymmetric broadside-coupled baluns, and a quad GS-connected diode. The fabricated doubler achieves a radio frequency bandwidth from 25 to 75 GHz with a maximum output power better than ┼3 dBm; the fundamental signal rejection is ranging from 32 to 59 dB, and only occupies a chip size of 0.24 mm
²
. To the knowledge of the authors, this double balanced frequency doubler is the first demonstration with an operating frequency up to 75 GHz in 0.18-μm CMOS technology and shows this silicon-based frequency doubler can compare with its GaAs counterpart.