A novel wafer-yield PDF model and verification with 90–150nm SOC chips

In this paper, we describe a new wafer yield distribution model, which agrees well with experiment using fabricated products with various process technologies. To investigate physical reasoning of the proposed model, we firstly measure effective defect density of chips regarding to spatial dependency in a wafer. It is clarified that the defect density near wafer edge is a couple of times larger than that at the rest of wafer area. Note that the increase of defect at wafer edge causes a significant yield loss in production process lines.