Analysis and Characterization of the Effects of Clock Jitter in A/D Converters for Subsampling

This paper investigates nature and effects of jitter on the clock edge that triggers the sample/hold used in direct-sampling and IF-sampling receiver architectures. The impact of the aperture uncertainty is theoretically discussed, simulated, and measured in the case of the high-frequency front-end of a 16-bit 65 MS/s analog-digital converter. Both characterizations of the phenomenon are considered: in the frequency domain [single-sideband to carrier ratio (SSCR), or phase noise] and in the time domain (aperture jitter). Theory and measurements are provided for the classic Leeson model, the spectrum caused by flicker noise, and the practically most relevant white noise case. In each instance, not only the degradation of the overall signal-to-noise ratio in presence of a large blocker is quantified; but a closed-form formula is introduced that rigorously quantifies the ldquospotrdquo scaling factor between the SSCR of the clock and the one of the sampled signal, for every offset frequency .