Spread spectrum clock generator

In this paper, we present a spread spectrum clock generator which has advantages of 1) Low cost: the loop filter of the SSCG is only 1/10 that of conventional approach. 2) Low jitter: the jitter induced by spectrum spread is only 1/2 that of recent publications. 3) Low power: Current consumption is 1/3 that of multiple phases PLL approach while keeping the smallest area. Moreover, the technique is digital implementation so it can be shrunk with voltage and process technology. The measurement shows that EMI reduction is 12.6dB and 8.2dB at 1% and 0.5% down spread with 1.5GHz clock output.