Key Integration Technologies for Nanoscale FRAMs

We discuss key technologies of 180 nm-node ferroelectric memories, whose process integration is becoming extremely complex when device dimension shrinks into a nano-scale. This is because process technology in ferroelectric integration does not extend to conventional shrink technology due to many difficulties of coping with MIM (Metal-Insulator-Metal) capacitors. The key integration technologies in ferroelectric random access memory (FRAM) comprise (1) etching technology to have less plasma damage; (2) stack technology for the preparation of robust ferroelectrics; (3) capping technology to encapsulate cell capacitors; and (4) vertical conjunction technology to connect cell capacitors to the plate-line. What has been achieved from these novel approaches is not only to have a peak-to-peak value of 675 mV in bit-line potential but to ensure sensing margin of 300 mV in opposite-state retention even after 1000 hours at 150 °C.