Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses

The influence of interconnects on processor performance and cost is becoming increasingly pronounced with technology scaling. In this paper, we present a fast compression scheme that exploits the spatial and temporal locality of addresses to dynamically compress them to different extents depending upon the extent to which they match the higher-order portions of recently-occurring addresses saved in a very small "compression cache" of capacity less than 500 bits. When a maximal match occurs, the address is compressed to the maximum extent and is transmitted on a narrow bus in one cycle. When a partial match occurs, one or more extra cycles are required for address transmission depending upon the extent of the partial match. To minimize this transmission cycle penalty (TCP), we use an efficient algorithm to determine the optimal set of partial matches to be supported in our partial match compression (PMC) scheme - we refer to this scheme as performance-optimized PMC (PO-PMC). A previously-proposed scheme called bus expander (BE) supports only a single, fixed-size match for compression. We show that all addresses that result in (maximal) matches in BE also result in the same in PMC, but the remaining addresses that are considered "no matches" in BE frequently result in partial matches in PMC, thus helping curtail the latter's TCP significantly. Across many SPEC CPU2000 integer and floating-point benchmarks, we find that average program performance improves by 3% when using PO-PMC compared to that when using BE. Further, we investigate how area slack arising from compression can be exploited for bus latency improvement by increasing inter-wire spacing. We find that, on the average, it can reduce bus latency by up to 84.63% and thereby improve program performance by about 16%.