Insights into Gate-Underlap Design in FinFETs for Ultra-Low Voltage Analog Performance

In this work, the usefulness of gate-underlap design to overcome the degradation of analog/rf FOMs (figures of merit) has been analyzed for ULV applications. For a device designed with d=5 nm/dec, the spacer widths in the range or 20- 50 nm represents lateral straggle values in the desired range of 10-15 nm independent of gate length to achieve significant improvement in analog FOMs. The optimal values of spacer widths range from 0.8L
_g
for 60 nm FinFETs to ~1.7L
_g
for 30 nm devices and even higher spacer-to-gate length ratios for 20 nm devices. The present work provides new opportunities for realizing future ULV analog/rf circuits.