A CMOS Current-Reused Transceiver with Stacked LNA and Mixer for WPAN

A low power transceiver is designed in 0.25 um CMOS technology. Designed transceiver is composed of CMOS PA and low-IF receiver architecture for high integration. To reduce the power dissipation, current-reused topology is used in Rx and up-conversion mixer. And, the simulated power consumption of PA is minimized by optimizing the size of power cells. The power consumptions are 31 mW and 69 mW for Rx and Tx paths, respectively, with 2.5 V supply voltage. Voltage conversion gain of designed receiver is varied from 11.5 to 27.5 dB. Output power is 14.7 dBm with 40 % of PAE at P1dB, and phase noise of QVCO is -122 dBc/Hzi@1MHz. These performances are sufficient for WPAN applications such as Zig-Bee and Bluetooth.