Design and Tradeoff Analysis of an Area Efficient Viterbi Decoder

The Viterbi decoder is widely used in digital communication systems. It performs the maximum-likelihood decoding of convolutional codes received from a noisy channel. Depending on the application (terrestrial, satellite, digital modems, digital cellular telephone applications and others) a Viterbi Decoder must be designed to meet specific requirements such as small area, high speed or maximum efficiency. This paper presents a novel architecture for Area Efficient Viterbi Decoder, which can be used for low bitrate applications. The design schedules all computations on less number of ACS processing elements as compared to parallel implementation assuming that a lot of clock cycles are available for decoding.