On Dealing With the Charge Trapped in Floating- Gate MOS (FGMOS) Transistors

This brief presents for the first time exhaustive experimental results of the only technique that has proven potential on eliminating residual trapped charge in floating gates without requiring any extra-circuitry or post-fabrication processing of the chip. The brief starts with a brief review of different techniques that have been used in the past to deal with the charge (sometimes to erase it, sometimes to program it) together with a description of the one used in the devices presented here. The validity of the latter is demonstrated with data obtained from 100 different devices, 50 of which make use of the technique. The results open up new application avenues for FGMOS devices, mostly in the context of low-power and low-voltage designs in which the potential of the transistor had already be proven but its feasibility, due to the uncertainty of the trapped charged, was questionable