A 2.2mW, Continuous-Time Sigma-Delta ADC for Voice Coding with 95dB Dynamic Range in a 65nm CMOS Process

A second order continuous time multibit (4bit) DeltaSigma-ADC for voice coding is implemented in a 65nm CMOS process. The dynamic range (DR) is 95dB over the voice bandwidth of 20-20 000Hz. Furthermore, by using a feed back architecture the need of an anti aliasing filter is eliminated. The input operational amplifier is chopped to eliminate flicker noise and offset. These improvements give way to a substantial simplification of the analog front end by allowing the absorption of the pre-amplifier and the antialiasing filter into the DeltaSigma-ADC. Thanks to the feedback structure the slew rate at the quantizer is limited and a power-efficient tracking ADC can be used. The total harmonic distortion (THD) is below -77dB at maximum input signal of 1.4Vpp. The ADC consumes 2.2mW from a 1.2V supply when clocked at 12MHz. The active area is 0.149 mm
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