Design methodologies and tools for circuit design in CMOS nanometer technologies

CMOS technology is evolving deeper and deeper into the nanometer era. Highly integrated systems are now being designed, many of which are mixed-signal, including analog and/or RF parts. Although the technological roadmap stays on track, the actual design of circuits in 65nm and below becomes a big bottleneck, that may even turn out to be a showstopper, if not addressed properly. Rising design complexities, tightening time-to-market constraints, leakage power, increasing technology tolerances, reducing supply voltages and worsening signal integrity conditions are key challenges that designers face. Novel types of devices, new process materials and new reliability issues are next on the horizon. EDA tools simply have become inevitable to design today's highly integrated systems (SoC or SiP). This invited paper presents an overview of the design methodologies and EDA tools that have been or are being developed to address the problems of designing such mixed-signal integrated systems. In particular, progress is described in modeling and simulation techniques for complex mixed-signal systems, in circuit and layout synthesis tools for analog/RF circuits, in yield optimization as well as in signal integrity analysis methods such as substrate noise and EMC/EMI analysis. This will be illustrated with several practical examples