Gate Workfunction Engineering in Bulk FinFETs for Sub-50-nm DRAM Cell Transistors

We proposed a new bulk FinFET that has a p
⁺
/n
⁺
poly-Si gate consists of p
⁺
region near the source and n
⁺
region near the drain and analyzed current-voltage characteristics and electric field profiles of 50-nm devices by changing the n
⁺
poly-Si gate length (L
_s
). For given gate length (L
_g
les50 nm) and fin body width (W
_fin
les30 nm), L
_s
was designed to satisfy the I
_off
requirement (i.e., 1 fA) of DRAM cell. Optimum L
_s
/L
_g
of 30-nm device was ~0.4 at a W
_fin
of 10 nm and ~0.2 at a W
_fin
of 15 nm