Effect of Input Sample Quantization on Dynamic Power in DSP Architectures

This paper analyzes the effect of varying the characteristic parameters of the DSP frontend, on the dynamic power consumed. No significant analysis has been carried out in this direction so far. The power reduction has always been a great challenge till date and it has been at the cost of system's performance. An efficient method of sampling and quantization that can bring down the power consumption is proposed. A heuristic based approach is provided to minimize the number of power consuming dynamic transitions, by an efficient sampling and quantization technique, for a specific input domain pertaining to ASIC (application specific) processors, without affecting their performance. A tool has been developed that can be tuned to the specific architecture, to fix up the parameters of the preprocessing stage optimally or can be tuned to have the most efficient architecture for the specified sampling frequency and type of quantization