A Sub-1V CMOS 2.5Gb/s Serial Link Transceiver Using 2X Oversampling

This paper presents the design of a 2.5Gb/s serial link transceiver with a power consumption of 70mW. With IV supply voltage, the transceiver achieves the bit error rate of 10
^-14
. A supply regulated PLL is shared by the transmitter and the receiver to facilitate the low-power and low-voltage design. The output jitter of the transmitter is 53.9ps peak-to-peak and the chip area is approximately 0.54 mm
²