SoC memory optimization using loop transformations

In today's embedded systems, the memory hierarchy is rapidly becoming a major factor in terms of power, performance and area. This is especially true for embedded multimedia applications using temporary multi-dimensional arrays that are typically used to store intermediate results during multimedia processing. In this paper, we introduce a new buffer allocation method to replace these temporary arrays and we combine it with loop fusion and tiling. The simple and effective method we present simultaneously applies tiling with fusion to a set of loop nests. Then, it replaces temporary arrays with smaller buffers containing the useful data. These new techniques allow to optimize memory space and reduce the number of cache misses. Our buffer allocation method is implemented in the PIPS compiler and the experiments are made on the StepNP simulator. They show that our technique yields a significant reduction in the number of data cache misses (on average, the data cache miss ratio is decreased by 14.3%)