Design of Mixed-Voltage I/O Buffer by Using NMOS-Blocking Technique

An nMOS-blocking technique for mixed-voltage I/O buffer realized with only 1timesV
_DD
devices can receive 2timesV
_DD
, 3timesV
_DD
, and even 4timesV
_DD
input signal without the gate-oxide reliability issue is proposed. In this paper, the 2timesV
_DD
input tolerant mixed- voltage I/O buffer by using the nMOS-blocking technique has been verified in a 0.25-mum 2.5-V CMOS process to serve 2.5/5-V mixed-voltage interface. The 3timesV
_DD
input tolerant mixed-voltage I/O buffer by using the nMOS-blocking technique has been verified in a 0.13-mum 1-V CMOS process to serve 1/3-V mixed-voltage interface. The proposed nMOS-blocking technique can be extended to design the 4timesV
_DD
, 5timesV
_DD
, and even 6timesV
_DD
input tolerant mixed-voltage I/O buffers. The limitation of the nMOS-blocking technique is the breakdown voltage of the pn-junction in the given CMOS process