Charge Trapping in High-$k$Gate Stacks Due to the Bilayer Structure Itself

Charge trapping at the interface between the two dielectric layers of a high-
$k$
gate stack is shown to be caused by Maxwell–Wagner instability, which is the following. The fact that the high-
$k$
and interfacial layers have different compositions means that they will also have different conductivities. Then, a gate bias will produce a discontinuity in current at their interface, causing charge to accumulate there until, in steady state, the same current flows through both layers. Maxwell–Wagner instability is shown to be coupled to a second instability, dielectric relaxation of the high-
$k$
layer; continuity of current in steady state requires that the electric fields in the two dielectric layers remain fixed, so the change in polarization of the high-
$k$
layer due to dielectric relaxation must be compensated for by the conduction of additional charge to the interface. Evidence for this behavior in high-
$k$
gate stacks is found in the thickness dependence of their dielectric relaxation current, with the correct dependence being obtained only from a model in which the two instabilities act simultaneously. Uniform dielectrics do not exhibit Maxwell–Wagner instability, and perfect crystals do not exhibit dielectric relaxation, making the ideal high-
$k$
gate dielectric a uniform single-layer perfect crystal bonded epitaxially to the Si substrate.