An Efficient Forward Biasing Body Bias Generator for Clock Delayed Domino Logic

A technique for improving domino logic is to use a variable threshold voltage keeper (VTVK), so that the keeper size may be increased to improve the noise-immunity without significantly increasing the power and the delay. In this work, a novel body bias generator with forward biasing capability is proposed for the VTVK scheme. Forward biasing the keeper source-body junction allows its threshold voltage to be lowered more than the zero-bias case. The advantages of this work over previous ones are single supply operation, and lower power delay product. The simulation results for a 0.18 μm CMOS technology show an improvement between 20% and 50% in power delay product at 10°C and 80°C respectively, over its previous counterpart.