A High Speed Interleaver for Emerging Wireless Communications

In this paper, a novel high-speed interleaver/deinterleaver is proposed. As data rates demanded in emerging communication applications increase, architectures for high-speed interleaving become essential. Three pipelined blocks comprise the interleaver to execute three permutation steps in high speed. The addition of Static Random Access Memories (SRAM) in stage 1 speeds up 24 times of interleaving efficiency. Operating at 200 MHz, this design accomplishes the overall throughput of 4.8 Gbps. The memory architecture of this interleaver can be configured to dynamically enable and disable memory blocks for low power consumption. This flexible design can perform both interleaving and deinterleaving functions. It supports different wireless standards as well, such as IEEE Standard (Std.) 802.16a, IEEE Std. 802.11a/g, and IEEE 802.11n proposal.