A fast locking DLL clock synthesizer

In this paper, a new programmable DLL (delay locked loop) based clock synthesizer is proposed. The DLL has several inherent advantages, such as no jitter accumulation, fast locking and easy integration of the loop filter. This paper proposes a new programmable DKK that includes a new PFD (phase frequency detector) and a new VCDL (voltage controlled delay line) to generate multiple clicks. It can generate clocks from 3 to 10 times of input clock with 5/spl mu/s locking time. The HSPICE simulation with 0.35/spl mu/m CMOS process verifies the proposed DLL operating in the frequency range of 300 MHz to 1 GHz.