Low power adiabatic multiplier with complementary pass-transistor logic

This paper presents a low-power multiplier based on adiabatic logic. Complementary pass-transistor adiabatic logic (CPAL) circuits are described, and the minimization of energy consumption is investigated by choosing the optimal size of the CPAL circuits. An 8/spl times/8-bit adiabatic multiplier is designed. The organization of the multiplier is identical to the conventional CMOS carry-save multiplier. All the circuits use CPAL to recover the charge of node capacitances. The power consumption of the proposed multiplier, based on CPAL, is significantly reduced, because the non-adiabatic energy loss of output loads has been eliminated using complementary pass-transistor logic for evaluation and transmission gates for energy-recovery. SPICE simulation results indicate energy savings of 70% as compared to the conventional CMOS implementation at 200 MHz.