A design of high speed double precision floating point adder using macro modules

Based on SMIC 0.18/spl mu/im 1.8V six-layer-metal CMOS process, we implement a 64-bit high speed pipelined floating point adder which satisfied IEEE 754 standard. After the critical path analysis of the pipelined structure, we custom design three macro modules in order to reduce critical path delay. After placement in datapath style and routing, we implement the layout of floating point adder. The chip area is 1.44 mm/sup 2/ and clock frequency is 518MHz.