Architecture and performance comparison of a statistic-based lottery arbiter for shared bus on chip

This paper presents a statistic-based priority strategy for dynamic priority arbiters and its application was investigated for the lottery arbiter. Two set M/spl times/M registers are proposed to record the arbitration history. The period of recording arbitration history is programmable. A randomized verification environment is used to do performance comparison for statistic-based and nonstatistic-based arbiters, the results show that the performance is improved when different master's request pattern is changed dynamically due to different programs running at system on chip and especially when the grants of different master's requests are correlated.