Concurrent chip-package design for 10GHz global clock distribution network

As a result of the continuous downscaling of the CMOS technology, on chip frequency for high performance microprocessor arrives 10GHz according to international technology roadmap for semiconductors (ITRS). In this paper, a 10GHz global clock distribution network using standing wave approach was analyzed on chip and package level. On chip level, a 10GHz standing wave oscillator (SWO) for global clock distribution network using 0.18/spl mu/m, 1P6M CMOS technology, is designed and analyzed. The simulation results show that the skew is well controlled (about 1ps) while the clock frequency variation is about 20% because power/ground return paths exist in different metal layers. On package level, we assume that the chip size is 20mm*20mm and flip-chip bonding technology is used. The simulation results show that the skew at random positions of the transmission line (spiral or serpentine shape) is within 10% of /spl tau//sub clk/ when the attenuation is about 1.5dB. For attenuation from 1.5dB to 6.7dB, the peak positions (n*/spl lambda//2) can be used as clock node. For the mesh and plane shape, the skew is controlled within 10% of /spl tau//sub clk/ using standing wave method.