Cost-effective integration of an FN-programmed embedded flash memory into a 0.25 /spl mu/m RF-BiCMOS technology

This paper presents a process technology for cost-effective integration of low-power flash-memories into a 0.25 /spl mu/m, high performance RF-BiCMOS process. Only 4 additional lithographic mask steps are used on top of the baseline BiCMOS process, leading to an in total 23 mask-level embedded flash BiCMOS process. Fowler-Nordheim-programmed stacked-gate and split-gate cells, suitable for medium density (Mbit) memories with programming times in the /spl mu/s-range and an endurance of >10/sup 5/ cycles are demonstrated. Peripheral high-voltage transistors with >10 V breakdown voltage are integrated without additional mask steps on top of the flash cell integration.