Asynchronous packet-switch for SoC

System-on-chip (SoC) design is facing increasing difficulties in its integration, global wiring delay and power dissipation. Interconnection network technology has the advantage over the conventional bus technology in its scalability; on the other hand, asynchronous circuit design technology may offer power saving and tackle the clock-skew problem. The combination of these two technologies therefore could be an optimal solution for the interconnection of SoC. In this paper, we focus on the implementation of packet-switch with asynchronous technology. The results of experiments run to evaluate several aspects of the packet-switch implementation are presented.