New VLSI design of a max-log-MAP decoder

This paper proposes a new design of a MAP decoder suitable for ASIC. The decoder architecture is parallel and pipeline, which makes the design applicable to bit rate communication systems. Max-log-MAP algorithm, which offers a good compromise between performance and complexity, is selected for implementation. One of the components of this algorithm, namely, the transition probability (/spl gamma/) calculation unit is studied and a new low complexity design of this unit is proposed. Overall decoder design is flexible to the transmission block lengths, which makes it suitable for variable length transmission systems.