ASIC design of IPSec hardware accelerator for network security

This paper describes ASIC design of IPSec hardware accelerator for network security which can execute tunnel-mode AH and ESP algorithm of IPSec protocol suite. The processor supports AES-128/192/256, TDES, HMAC-MD5 and HMAC-SHA-1 algorithm to encrypt and authenticate the packet data and operates as hardware coprocessor to accelerate cryptographic routine of FreeS/WAN software. The IPSec hardware accelerator consists of AMBA interface, 2KB packet memory, parameter registers, global controller, and cryptographic module. It was designed using 0.25/spl mu/m CMOS standard cell library and consists of about 78K gates and 2KB memory. Its throughput of ESPAES128-HMAC-SHA1 operation is approximately 200 Mbps at 125MHz for 120-byte test packet.