An 8-bit 250MSPS CMOS pipelined ADC using open-loop architecture

This paper describes some design techniques for high speed and low power pipelined 8-bit 250MSPS ADC. To perform high-speed operation with relatively low power consumption, open loop architecture is adopted, while closed loop architecture (with MDAC) is used in conventional pipeline ADC. To reduce the power consumption and the die area, the number of amplifiers in each stage are optimized and reduced with proposed zero-crossing point generation method. At 250MHz sampling rate, measurement results show that the power consumption is 150mW including digital logic with 1.8V power supply. And the proposed ADC achieves 38dB (SNDR) with input frequency up to 125-MHz and input range of 1.2Vpp (Differential). The ADC is designed using a 0.18 /spl mu/m 6-Metal 1-Poly CMOS process and occupies an area of 900 /spl mu/m /spl times/ 500 /spl mu/m.