Key design techniques of a 40 ns 16 Kbit embedded EEPROM memory

A 2K/spl times/8 bit EEPROM memory, which operates with a single 3.3 V power supply based on SMIC 0.35 /spl mu/m EEPROM process, has been developed. Several key design techniques are summarized. An improved read out circuit that consists of SA (sense amplifier), bit line decoding and an optimized logic circuit to minimize the read access time, is described particularly, as well as the approaches to optimize the program operation and to generate on-chip high voltage. A 40 ns typical read access time and 2 ms page programming time are achieved. The active and standby currents are 10 mA and 100 /spl mu/A respectively.