Packaging process induced retention degradation of 256 Mbit DRAM with negative wordline bias

The data retention time performance of 256 Mbit DRAM is degraded even in a 250/spl deg/C packaging process. The retention time degradation is strongly dependent on the negative wordline voltage and operation temperature. Trap-assisted gate induced drain leakage is proposed as the mechanism for the retention degradation based on electrical testing and simulation. It is believed that silicon-hydrogen bond breaking and moving at the gate and drain overlap region of an array transistor is the root cause of retention degradation.