Thermal assessment of RF-integrated LTCC front end modules

The thermal performance of front end module (FEM) incorporating low-temperature cofired ceramic (LTCC) substrate is investigated. An infrared microscope system was used to measure device surface temperature with both RF and dc power. Various duty cycles (25% to 100%) were applied to characterize the thermal performance of the device for different power densities. The maximum junction temperature occurs at the second stage: under dc powering at 100% duty cycle, it reaches 134/spl deg/C. The comparison between numerical and experimental data indicates good agreement, with less than 10% difference in the peak temperature values. When replacing the common 2-layer organic substrate with a 14-layer LTCC substrate and silver paste metallization, the peak junction temperature reaches 130.1/spl deg/C, /spl sim/51% higher compared to the baseline case using a 2-layer organic substrate with copper metallization. However, by increasing the silver paste thermal conductivity from 90 to 350 W/mK, a significant drop in peak temperatures occurs, indicating the impact on the module's overall thermal performance. For the case with 350 W/mK, the peak temperature reaches 82.9/spl deg/C, almost 3% lower than the baseline case with 2-layer organic substrate. The top metal layer thickness (10 versus 30 /spl mu/s) contributed only to 5%-8% change in the peak junction temperature. An improved FEM design incorporates a higher thermal conductivity silver paste material (300 W/mK) and a new thermal via array structure (25 vias, 150 /spl mu/s in diameter each) in the LTCC substrate. The module junction temperature reaches 96/spl deg/C (based on 25/spl deg/C reference temperature and 100% duty cycle), corresponding to a junction-to-substrate (R/sub js/) thermal resistance of 14/spl deg/C/W. Further study reveals that 20% voiding placed at the die center has no impact on FEM thermal performance, while the voiding placed at the die corner (under the heat dissipating stages) increases the stage peak temperature by more than 40/spl deg/C. The last part of this paper focuses on several designs to reduce the manufacturing and assembly costs, while maintaining reasonable FEM thermal performance. Analyses suggest that two particular designs provide the optimal thermal performance when reducing the thermal via number/costs by almost 40%.