Design and implementation of an RNS-based 2-D DWT processor

Discrete wavelet transform has been incorporated as part of the JPEG2000 image compression standard and is used in many consumer imaging products. This paper presents a 2-dimensional biorthogonal DWT processor design based on the residue number system. The symmetric extension scheme is employed to reduce distortion at image boundaries. Hardware complexity reduction and utilization improvement are achieved by hardware sharing. Our implementation results show that the design is able to fit into a 1,000,000-gate FPGA device and is able to complete a first level 2-D DWT decomposition of a 32/spl times/32-pixel image in 205 /spl mu/s.