Influence of wiring parasitics on CMOS logic gates

This paper investigates the influence of parasitic interconnections on high speed logic gates. A complementary metal oxide semiconductor logic (CMOS) gate, a high speed source coupled logic (SCL) gate and a low power SCL gate are compared. The important impact of the wiring parasitics on the speed performances is pointed out. The results are confirmed with test circuits, fabricated on commercial 0.25 /spl mu/m CMOS technology.