Symbol synchronization technique in COFDM systems

In this paper we focus our research on the symbol timing synchronization technique in COFDM systems. A new method utilizing pilots to do coarse symbol timing is proposed. It overcomes the problem of fluctuation of the estimated symbol start position with cyclic prefix correlation method. The symbol timing error with the proposed method is within only /spl plusmn/10 samples. Different from previous algorithms in , we utilize the known pilot information to estimate the residual symbol timing offset with low system complexity. This paper also proposes a new control model for the sampling clock adjustment, different from the phase-locked loop (PLL), or delay-locked loop (DLL) method. The simulation and correspondent Field Programmable Gate Array (FPGA) circuit through test in HDTV prototype in Team of Engineering Expert Group (TEEG) proves its feasibility and availability. The proposed method is also suitable for burst mode transmission systems such as Wireless Local Area Network (WLAN) and Fixed-Broadband Wireless Access (F-BWA).