New junction concepts for sub-50 nm CMOS transistors: slim spacers and Ni silicide

In this paper, we evaluate the potential of two concepts aiming at the vertical and horizontal reengineering of the S/D junctions of sub-50 nm-CMOS transistors: slim S/D spacers and Ni silicide. We demonstrate the benefit of the lateral spacer size reduction in terms of device performance. For the junction silicidation with Ni, we find electrically equivalent results while the silicidation depth is reduced by 50% with respect to the Co reference. This will enable the use of shallower S/D junctions giving a maximum DIBL and SCE control - an approach, which is especially interesting in combination with slim spacers.