Mechanical stress control in a VLSI-fabrication process: a method for obtaining the relation between stress levels and stress-induced failures

An ideal fabrication process is designed to minimize mechanical stress in semiconductor devices and to improve device reliability. Mechanical stress levels were predicted by in-house simulations supported by a thin-film database. These stress levels were correlated with stress-induced defects by TEM analysis supported by fail bit addressing on matured megabit SRAMs. Amorphous-doped silicon film with various annealing temperatures were used for the gate electrode to change the mechanical stress in devices and to get the direct relationship between predicted stress levels and stress related defects. The authors describe brief guidelines for suppressing dislocations in the small geometry shallow-trench isolation process utilizing this system. Polysilicon thickness in the W-polycide gate electrode is designed to minimize mechanical stress in the gate oxide and to suppress the gate oxide failure in probe and class tests. Moreover, critical stress generates dislocations during post source/drain ion implantation anneal obtained by a ball indentation method. This indicated that lower temperature anneal is effective in suppressing the dislocations. A two-step anneal was introduced to suppress dislocations and to enable higher ion activation.