An edge-defined nano-lithography technique suitable for low thermal budget process and 3-D stackable devices

Edge-defined nano-meter scale lines patterned in silicon using 1/spl mu/m optical lithography with standard materials and processing equipment are compatible with low thermal budget 3-D IC processes. A chemical vapor deposition (CVD) process is used to define spacers, around optically registered edges, that are combined with the photoresist mask to pattern underlying layers. Good control of CVD and dry etching enables patterning of features from 180 nm to 180 nm. Local critical dimension (CD) variations of up to /spl sim/7 nm are observed, based on CD-SEM analysis. Spacer film roughness, oxide dry etch, and edge registration lithography contribute to CD variation and line-edge roughness.