A 5 GHz CMOS RF mixer in 0.18 /spl mu/m CMOS technology

In this paper, we present in this paper a CMOS down-conversion double balanced mixer for 5 GHz radio applications. The mixer is derived from the basic Gilbert cell multiplier and has been implemented in a standard 0.18 /spl mu/m CMOS technology. The proposed topology does not contain any tail current branches, but include on-chip bias circuit. It has been designed for low power highly integrated applications. It achieves a gain of 20.91 dB, input 1dB compression point of -19.71 dBm, noise figure (NF) of 9.1 dB, and IIP3 of -13.6 dBm, while dissipating 3.95 mW at 1.8 V.