A low-voltage low-noise CMOS digital family

A CMOS logic family is proposed. The primary characteristic of this logic family is the low voltage operation (V/sub DD/ between one and two transistor threshold voltages (V/sub T/s), with a typical V/sub DD/ = 1.5 V/sub T/). While operating at this reduced power supply, low noise and high performance (such as high speed, low power, and high noise margins) are achieved.