Highly efficient digital CMOS accelerator for image and graphics processing

This paper presents a novel high-bandwidth digital accelerator for image and graphics processing applications. The proposed architecture outperforms previously proposed processing-in-memory architectures in speed, area and power by up to several orders of magnitude. Several variations of the design have been implemented in 2.5 V 0.25 /spl mu/m and 1.8 V 0.18 /spl mu/m CMOS technology.