Precise thickness control for ultra-thin SOI in ELTRAN/spl reg/ SOI-Epi/spl trade/ wafer

In ultra-thin-SOI MOSFET, especially in fully depleted operation, threshold voltage is strongly affected by SOI thickness in addition to dopant concentration. For instance, 5 % of tolerance is proposed in ITRS2001. This paper discusses the SOI thickness uniformity in various periods of undulations, especially focusing on ELTRAN SOI-Epi wafers, that is formed by bonding of epitaxial layer on porous Si, splitting, etching back of porous Si, and final Hz annealing to smooth the SOI surface.