Design techniques for low power high bandwidth upconversion in CMOS

An upconvertor topology for low power, high bandwidth applications is presented. Using specific circuit techniques and local circuit-level optimization, the power consumption of the total system comprising an on-chip LC-type VCO, a polyphase network quadrature generator, a linear mixer block and an RF-current buffer, has been minimized. A chip has been designed and manufactured in a 0.25 /spl mu/m CMOS technology. The VCO oscillates between 1.68 GHz and 2 GHz. Driven by an external LO, the transmitter operates from 900 MHz up to 2 GHz. At 2 GHz, the upconvertor transmits -12 dBm into 50 /spl Omega/ with a linearity of more than -35 dBc for base band signals up to 33 MHz.